Robust sound localization in 0.18 µm CMOS

An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS

A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process

This paper presents a four-stage CMOS distributed amplifier (DA) design implemented in standard 0.18 μm CMOS technology. The proposed design eliminates the need for transmission line capacitors and, consequently, uses significantly smaller spiral inductors compared with the previous designs. Using the minimum size inductor, the bandwidth of the amplifiers is extended, and the quality factors of...

Design of 1 V Operating Fully Differential OTA Using NMOS Inverters in 0.18 µm CMOS Technology

Abstract: A 1 V operating fully differential OTA is presented. We designed a 1 V operating fully differential OTA using NMOS inverters in place of traditional differential pair. To obtain high voltage gain, a two stage configuration has been used in which the first stage has feedforward to cancel common-mode signal and the second stage has commonmode feedback. This OTA was fabricated by 0.18 μm...

A New Solution to Analysis of CMOS Ring Oscillators

New equations are proposed for frequency and amplitude of a ring oscillator. The method is general enough to be used for all types of delay stages. Using exact largesignal circuit analysis, closed form equations for estimating the frequency and amplitude of a high frequency ring oscillator are derived as an example. The method takes into account the effect of various parasitic capacitors to...

A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops

A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-topeak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of –93.5 dBc/Hz at 1-MHz offset. The cor...